The PS3's 3.2 GHz
Cell processor, developed jointly by Sony, Toshiba and IBM ("SIT"), is an implementation to dynamically assign physical processor cores to do different types of work independantly. It has a PowerPC-based "Power Processing Element" (PPE) and six accessible 3.2 GHz
Synergistic Processing Elements (SPEs), a seventh runs in a special mode and is dedicated to OS security, and an eighth disabled to improve production yields. The PPE, SPE's and other elements ("units") are connected via an Element Interconnect Bus which serves to connect all of the units in a ring-style bus. The PPE has a 512KB
level 2 cache and one
VMX vector unit. Each of the SPEs is a
RISC processor with 128 128-bit
SIMD GPRs and superscalar functions. Each SPE contains 256KB of non-cached memory (local storage, "LS") that is shared by program code and work data. SPEs may access more data in the main memory using DMA. The floating point performance of the whole system (CPU + GPU) is reported to be 2.18
TFLOPS[38]. PlayStation 3's Cell CPU achieves 218 GFLOPS single precision
float and is reported at around
26 GFLOPS double precision. The PS3 will ship with 256 MB of
Rambus XDR DRAM, clocked at CPU die speed.
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